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A Survey of Baseband Architecture for Software Defined Radio
This paper is a survey of recent works that proposes a baseband processor architecture for software defined radio. A classification of different approaches is proposed. The performance of each architecture is also discussed in order to clarify the suitable approaches that meet software-defined radio constraints.
Digital Object Identifier (DOI):


[1] J. Mitola, “Software Radios Survey, Critical Evaluation and Future
[2] Micka ̈ l Dardaillon, Kevin Marquet , Tanguy Risset, Antoine Scherrer , “Software Defined Radio Architecture Survey for Cognitive Testbeds”, IWCMC, 2012.
[3] Omer Anjum1*, Tapani Ahonen1, Fabio Garzia1, Jari Nurmi1, Claudio Brunelli2 and Heikki Berg2, “State of the art baseband DSP platforms for Software Defined Radio: A survey”, EURASIP Journal on Wireless Communications and Networking, 2011.
[4] Martin Palkovic, Praveen Raghavan, Perre, Li, and Francky Catthoor, “Future Software-Defined Radio Platforms and Mapping Flows”, IEEE signal processing magazine, march 2010.
[5] V. Saito and V. Sugiyama, “Single-Chip Baseband Signal Processor for Software-Defined Radio,” FUJITSU Sci. Tech. J, vol. 42, no. 2, pp. 240–247, 2006.
[6] Yi Ge, Mitsuru Tomono, Makiko Ito, Yoshio Hirose, “High-performance and Low-power Consumption Vector Processor for LTE Baseband LSI”, FUJITSU Sci. Tech. J., Vol. 50, No. 1, January 2014.
[7] Deepak Revanna, Omer Anjum, ManueleCucchi, Roberto Airoldi, JariNurmi, “A Scalable FFT Processor Architecture for OFDM Based Communication Systems”, Department of Electronics and Communications Engineering Tampere University of Technology, Finland, 2013.
[8] Jiang Weipeng He ZhiqiangDuan Ran Wang Xinglin, “Major Optimization Methods for TD-LTE Signal Processing based on General Purpose Processor”, CHINACOM, 2012.
[9] Xin Wei, Xin Qi, Limin Xiao, Zhiyuan Shi, Lianfen Huang, “Software-Defined Radio Based On Cortex-A9”, School of Information Science &Technology, Xiamen University, State Key Laboratory on Microwave and Digital Communications Tsinghua National, Laboratory for Information Science and Technology, Tsinghua University Beijing China, 2012.
[10] Michael Schwall, Stefan Nagel, Friedrich K. Jondral, “Code Parallelization for Multi-Core Software Defined Radio Platforms with OpenMP”, 2011.
[11] Kun Tan, He Liu, Jiansong Zhang, Yongguang Zhang, Ji Fang, Geoffrey M. Voelker, “Sora: High-Performance Software Radio Using General-Purpose Multi-Core Processors”, 2009.
[12] Yuxiang Li, Ji Fang, Kun Tan, Jiansong Zhang, Qimei Cui, Xiaofeng Tao, “Soft-LTE: A Software Radio Implementation of 3GPP Long Term Evolution Based on Sora Platform”, In ACM MobiCom 2009.
[13] Peng Guo, Xin Qi, Limin Xiao, Shidong Zhou, “A Novel GPP-based, Software Defined Radio Architecture”, 2012.
[14] Saehee Bang, ChiyoungAhn, Yong Jin, Seungwon Choi, John Glossner, Sungsoo Ahn, “Implementation of LTE system on an SDR platform using CUDA and UHD”. Springer Science, Business Media New York, 2013.
[15] Camille Jalier, Didier Lattard and Ahmed Amine Jerraya CEA, LETI, Gilles Sassatelli, Pascal Benoit and Lionel Torres, “Heterogeneous vs Homogeneous MPSoC Approaches for a Mobile LTE Modem”, 2010.
[16] Fabien Clermidy, Christian Bernard, Romain Lemaire, Jerome Martin, Ivan Miro-Panades, YvainThonnart, Pascal Vivet, Norbert Wehn, “A 477mW NoC-Based Digital Baseband for MIMO 4G SDR”, 2010.
[17] Benedikt Noethen, Oliver Arnold, Esther Pérez Adeva, Tobias Seifert, Erik Fischer, Steffen Kunze, Emil Matúš, Gerhard Fettweis, Holger Eisenreich, Georg Ellguth, Stephan Hartmann, Sebastian Höppner, Stefan Schiefer, Jens-Uwe Schlüßler, Stefan Scholze, Dennis Walter, René Schüffny, “A 105GOPS 36mm2 Heterogeneous SDR MPSoC with Energy-Aware Dynamic Scheduling and Iterative Detection-Decoding for 4G in 65nm CMOS”, 2014 IEEE International Solid-State Circuits Conference.
[18] T. Limberg, M. Winter, M. Bimberg, R. Klemm, E. Matus, M. Tavares, G. Fettweis, H. Ahlendorf, and P. Robelly, “A fully programmable 40 GOPS SDR single chip baseband for LTE/WiMAX terminals,” in Solid-State Circuits Conference, ESSCIRC. 34th European, (Edinburgh, Scotland), pp. 466–469, IEEE, Sept. 2008.
[19] Toshiki Takeuchi, Hiroyuki Igura, Masao Ikekawa, “Stream-Access-Oriented Baseband Signal Processors for SDR”, System IP Core Research Labs., NEC Corporation Kawasaki, Japan, 2012.
[20] V. Derudder, B. Bougard, A. Couvreur, A. Dewilde, S. Dupont, L. Folens, L. Hollevoet, F. Naessens, D. Novo, P. Raghavan, T. Schuster, K. Stinkens, J.-W. Weijers, and L. Van der Perre, “A 200mbps+ 2.14nj/b digital baseband multi-processor system-on-chip for SDRS,” in Proc of VLSI Symposum, June 2009.
[21] Jeroen Declerck, Praveen Raghavan, Frederik Naessens, Tom Vander Aa, Lieven Hollevoet, Antoine Dejonghe, Liesbet Van der Perre, IMEC, “SDR Platform for 802.11n and 3-GPP LTE”, 2010.
[22] C. Schmidt-Knorreck, R. Pacalet, A. Minwegen, U. Deidersen, T. Kempf ,R. Knopp, G.Ascheid, “Flexible Front-End Processing For Software Defined Radio Applications Using Application Specific Instruction-Set Processors”, 2012.
[23] “Flexible baseband architectures for future wireless systems,” in Digital System Design Architectures, Methods and Tools, 2008. DSD ’08. 11th EUROMICRO Conference on, Sept. 2008, pp. 39–46.
[24] N.-u.-I. Muhammad, R. Rasheed, R. Pacalet, et al. U. Ramacher, W. Raab, U. Hachmann, D. Langen, J. Berthold, R. Kramer, A. Schackow, C. Grassmann, M. Sauermann, P. Szreder, F. Capar, G. Obradovic, Kang Lee, Eugene Weber, Ray Kuhn, John Harrington, “Architecture and Implementation of a Software-Defined Radio Baseband Processor”, 2011.
[25] Tomoya Suzuki, Hideki Yamada, Toshiyuki Yamagishi, Daisuke Takeda,KojiHorisaki, Toshio Fujisawa, YasuoUnekawa, Toshiba, Tom Vander Aa, Liesbet Van der Perre, IMEC, “High-Throughput, Low-Power Software-Defined Radio Using Reconfigurable Processors”, 2011.
[26] KitaekBae, Peng Xue, NavneetBasutkar, and Ho Yang, “Software Design of Giga-bit WLAN on Coarse Grained Reconfigurable Array Processors”, 2013.
[27] Praveen Kumar P Dr.Noor Mohammad S K , “Reconfigurable baseband modulator for Software Defined Radio ”, 2013.
[28] R. Tessier, and W. Burleston, “Reconfigurable computing for digital signal processing: a survey” Journal of VLSI Signal Processing, 2001.
[29] Amiya Karmakar Amitabha Sinha, “A Novel Architecture of a Reconfigurable Radio Processor for Implementing Different Modulation Schemes”, 2011.
[30] Ke He & Louise Crockett & Robert Stewart, “Dynamic Reconfiguration Technologies Based on FPGA in Software Defined Radio System”, 2011.
[31] Botao Zhang, Hengzhu Liu, Shixian Wang, Dongpei Li u, “Application Specific Parallel Memory Architecture for Software Defined Radio”, 2011.
[32] Julien Heulot, JaniBoutellier, Maxime Pelcat, Jean-Francois Nezan, Slaheddine Aridhi, “Applying the Adaptive Hybrid Flow-Shop Scheduling Method to Schedule a 3GPP LTE Physical Layer Algorithmonto Many-Core Digital Signal Processors, 2013.
[33] Firew Siyoum, Marc Geilen, Orlando Moreira, Rick Nas, Henk Corporaal, Eindhoven University of Technology, ST-Ericsson Eindhoven, “Analyzing Synchronous Dataflow Scenarios for Dynamic Software-defined Radio Applications”, 2011.
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