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10010073
Cascaded H-Bridge Five Level Inverter Based Selective Harmonic Eliminated Pulse Width Modulation for Harmonic Elimination
Abstract:
In this paper, selective harmonic elimination pulse width modulation technique is employed to eliminate lower order harmonics like third by determination of solving non-linear equations. The cascaded H-bridge five level inverter is driven by the Peripheral Interface Controlled (PIC) Microcontroller 16F877A. The performance of single phase cascaded H-bridge five level inverter with relevant to harmonics and a variety of switches with solar cell as its input source is simulated by employing MATLAB/Simulink. A hardware model is developed to verify the performance of the developed system.
Digital Object Identifier (DOI):

References:

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