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Reversible Binary Arithmetic for Integrated Circuit Design
Application of reversible logic in integrated circuits results in the improved optimization of power consumption. This technology can be put into use in a variety of low power applications such as quantum computing, optical computing, nano-technology, and Complementary Metal Oxide Semiconductor (CMOS) Very Large Scale Integrated (VLSI) design etc. Logic gates are the basic building blocks in the design of any logic network and thus integrated circuits. In this paper, reversible Dual Key Gate (DKG) and Dual key Gate Pair (DKGP) gates that work singly as full adder/full subtractor are used to realize the basic building blocks of logic circuits. Reversible full adder/subtractor and parallel adder/ subtractor are designed using other reversible gates available in the literature and compared with that of DKG & DKGP gates. Efficient performance of reversible logic circuits relies on the optimization of the key parameters viz number of constant inputs, garbage outputs and number of reversible gates. The full adder/subtractor and parallel adder/subtractor design with reversible DKGP and DKG gates results in least number of constant inputs, garbage outputs, and number of reversible gates compared to the other designs. Thus, this paper provides a threshold to build more complex arithmetic systems using these reversible logic gates, leading to the enhanced performance of computing systems.
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[1] R. Landauer, “Irreversibility and Heat Generation in the Computing Process”, IBM J. Research and Development, vol. 3, pp. 183-191, July 1961.
[2] C. H. Bennett, “Logical Reversibility of Computation”, IBM J. Research and Development, pp.525-532, November 1973.
[3] Thapliyal, H. and Ranganathan, N., “Design of Reversible Sequential Circuits optimizing Quantum Cost, Delay, and Garbage Outputs”, 2010 ACM J. Emerg. Technol. Comput. Syst. 6, 4, Article 14, (December 2010), 31 pages.
[4] D. Krishnaveni, M. Geetha Priya, ‘A Novel Design of Reversible Serial and Parallel Adder/ Subtractor’ IJEST vol 3,No 3, March 2011, pg 2280-2288.
[5] D. Krishnaveni, M. Geetha Priya, K. Baskaran, “Design of an Efficient Reversible 8x8 Wallace Tree Multiplier” World Applied Sciences Journal 20 (8): 1159-1165, © IDOSI Publications, 2012
[6] H. R. Bhagyalakshmi and M. K. Venkatesha, ‘An improved design of a multiplier using reversible logic gates’, International Journal of Engineering Science and Technology Vol. 2(8), 2010, 3838-3845
[7] D. Krishnaveni, M. Geetha Priya,‘A Novel Reversible EX-NOR SV Gate and Its Application’ vol 5, LNNS series, Springer, pg 105-114.
[8] Thapliyal, H. and Ranganathan, N. (2011) A New Design of the Reversible Subtractor Circuit. Proceedings of IEEE International Conference on Nanotechnology, Portland, 15-18 August 2011, 1430-1435.
[9] Md. Saiful Islam,’ A Novel Quantum Cost Efficient Reversible Full Adder Gate in Nanotechnology’
[10] M. Surekha,’ Efficient Approaches for Designing Quantum Costs of Various Reversible Gates’, International Journal of Engineering Studies. ISSN 0975-6469 Volume 9, Number 1 (2017), pp. 57-78
[11] Maii T. Emam, Layle A. A. Elsayed, ‘Reversible Full Adder/ Subtractor’ Symbolic and Numerical Methods, Modeling and Applications to Circuit Design. (SM2ACD), 2010 XIth International Workshop on. IEEE, 2010
[12] Neeraj Kumar Misra, Mukesh Kumar Kushwaha, Subodh Wairya,’ Cost Efficient Design of Reversible Adder Circuits for Low Power Applications’, International Journal of Computer Applications (0975 – 8887) Volume 117 – No. 19, May 2015
[13] V.Kamalakannan1, Shilpakala.V2, Ravi. H. N,’ Design of Adder/ Subtractor Circuits Based On Reversible Gates’, International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering Vol. 2, Issue 8, August 2013, ISSN 2320 – 3765
[14] Rangaraju H G, Venugopal U, Muralidhara K N, Raja K B, “Low Power Reversible Parallel Binary Adder/Subtractor”, International Journal of VLSI design & Communication Systems, Vol. 1, No. 3, pp. 23-34, 2010
[15] P. K. Lala, J. P. Parkerson, P. Chakraborty,’ Adder Designs using Reversible Logic Gates’, WSEAS Transactions on Circuits and Systems, Issue 6, Volume 9, June 2010, pg-369-378
[16] J.W. Bruce, M.A. Thornton, L. Shivakumaraiah, P.S. Kokate, X. Li, ‘Efficient Adder Circuits Based on a Conservative Reversible Logic Gate’
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