A Survey of Field Programmable Gate Array-Based Convolutional Neural Network Accelerators
With the rapid development of deep learning, neural network and deep learning algorithms play a significant role in various practical applications. Due to the high accuracy and good performance, Convolutional Neural Networks (CNNs) especially have become a research hot spot in the past few years. However, the size of the networks becomes increasingly large scale due to the demands of the practical applications, which poses a significant challenge to construct a high-performance implementation of deep learning neural networks. Meanwhile, many of these application scenarios also have strict requirements on the performance and low-power consumption of hardware devices. Therefore, it is particularly critical to choose a moderate computing platform for hardware acceleration of CNNs. This article aimed to survey the recent advance in Field Programmable Gate Array (FPGA)-based acceleration of CNNs. Various designs and implementations of the accelerator based on FPGA under different devices and network models are overviewed, and the versions of Graphic Processing Units (GPUs), Application Specific Integrated Circuits (ASICs) and Digital Signal Processors (DSPs) are compared to present our own critical analysis and comments. Finally, we give a discussion on different perspectives of these acceleration and optimization methods on FPGA platforms to further explore the opportunities and challenges for future research. More helpfully, we give a prospect for future development of the FPGA-based accelerator.
Implementation of Edge Detection Based on Autofluorescence Endoscopic Image of Field Programmable Gate Array
Autofluorescence Imaging (AFI) is a technology for detecting early carcinogenesis of the gastrointestinal tract in recent years. Compared with traditional white light endoscopy (WLE), this technology greatly improves the detection accuracy of early carcinogenesis, because the colors of normal tissues are different from cancerous tissues. Thus, edge detection can distinguish them in grayscale images. In this paper, based on the traditional Sobel edge detection method, optimization has been performed on this method which considers the environment of the gastrointestinal, including adaptive threshold and morphological processing. All of the processes are implemented on our self-designed system based on the image sensor OV6930 and Field Programmable Gate Array (FPGA), The system can capture the gastrointestinal image taken by the lens in real time and detect edges. The final experiments verified the feasibility of our system and the effectiveness and accuracy of the edge detection algorithm.
FPGA Implementation of the BB84 Protocol
The development of a quantum key distribution (QKD) system on a field-programmable gate array (FPGA) platform is the subject of this paper. A quantum cryptographic protocol is designed based on the properties of quantum information and the characteristics of FPGAs. The proposed protocol performs key extraction, reconciliation, error correction, and privacy amplification tasks to generate a perfectly secret final key. We modeled the presence of the spy in our system with a strategy to reveal some of the exchanged information without being noticed. Using an FPGA card with a 100 MHz clock frequency, we have demonstrated the evolution of the error rate as well as the amounts of mutual information (between the two interlocutors and that of the spy) passing from one step to another in the key generation process.
FPGA Implementation of Adaptive Clock Recovery for TDMoIP Systems
Circuit switched networks widely used until the end of the 20th century have been transformed into packages switched networks. Time Division Multiplexing over Internet Protocol (TDMoIP) is a system that enables Time Division Multiplexing (TDM) traffic to be carried over packet switched networks (PSN). In TDMoIP systems, devices that send TDM data to the PSN and receive it from the network must operate with the same clock frequency. In this study, it was aimed to implement clock synchronization process in Field Programmable Gate Array (FPGA) chips using time information attached to the packages received from PSN. The designed hardware is verified using the datasets obtained for the different carrier types and comparing the results with the software model. Field tests are also performed by using the real time TDMoIP system.
The DAQ Debugger for iFDAQ of the COMPASS Experiment
In general, state-of-the-art Data Acquisition Systems
(DAQ) in high energy physics experiments must satisfy high
requirements in terms of reliability, efficiency and data rate capability.
This paper presents the development and deployment of a debugging
tool named DAQ Debugger for the intelligent, FPGA-based Data
Acquisition System (iFDAQ) of the COMPASS experiment at CERN.
Utilizing a hardware event builder, the iFDAQ is designed to be
able to readout data at the average maximum rate of 1.5 GB/s of
the experiment. In complex softwares, such as the iFDAQ, having
thousands of lines of code, the debugging process is absolutely
essential to reveal all software issues. Unfortunately, conventional
debugging of the iFDAQ is not possible during the real data taking.
The DAQ Debugger is a tool for identifying a problem, isolating
the source of the problem, and then either correcting the problem
or determining a way to work around it. It provides the layer
for an easy integration to any process and has no impact on the
process performance. Based on handling of system signals, the
DAQ Debugger represents an alternative to conventional debuggers
provided by most integrated development environments. Whenever
problem occurs, it generates reports containing all necessary
information important for a deeper investigation and analysis. The
DAQ Debugger was fully incorporated to all processes in the iFDAQ
during the run 2016. It helped to reveal remaining software issues
and improved significantly the stability of the system in comparison
with the previous run. In the paper, we present the DAQ Debugger
from several insights and discuss it in a detailed way.
The Communication Library DIALOG for iFDAQ of the COMPASS Experiment
Modern experiments in high energy physics impose
great demands on the reliability, the efficiency, and the data rate
of Data Acquisition Systems (DAQ). This contribution focuses on
the development and deployment of the new communication library
DIALOG for the intelligent, FPGA-based Data Acquisition System
(iFDAQ) of the COMPASS experiment at CERN. The iFDAQ
utilizing a hardware event builder is designed to be able to readout
data at the maximum rate of the experiment. The DIALOG library is a
communication system both for distributed and mixed environments,
it provides a network transparent inter-process communication layer.
Using the high-performance and modern C++ framework Qt and its
Qt Network API, the DIALOG library presents an alternative to
the previously used DIM library. The DIALOG library was fully
incorporated to all processes in the iFDAQ during the run 2016.
From the software point of view, it might be considered as a
significant improvement of iFDAQ in comparison with the previous
run. To extend the possibilities of debugging, the online monitoring
of communication among processes via DIALOG GUI is a desirable
feature. In the paper, we present the DIALOG library from several
insights and discuss it in a detailed way. Moreover, the efficiency
measurement and comparison with the DIM library with respect to
the iFDAQ requirements is provided.
Field-Programmable Gate Array Based Tester for Protective Relay
The reliability of the power grid depends on the successful operation of thousands of protective relays. The failure of one relay to operate as intended may lead the entire power grid to blackout. In fact, major power system failures during transient disturbances may be caused by unnecessary protective relay tripping rather than by the failure of a relay to operate. Adequate relay testing provides a first defense against false trips of the relay and hence improves power grid stability and prevents catastrophic bulk power system failures. The goal of this research project is to design and enhance the relay tester using a technology such as Field Programmable Gate Array (FPGA) card NI 7851. A PC based tester framework has been developed using Simulink power system model for generating signals under different conditions (faults or transient disturbances) and LabVIEW for developing the graphical user interface and configuring the FPGA. Besides, the interface system has been developed for outputting and amplifying the signals without distortion. These signals should be like the generated ones by the real power system and large enough for testing the relay’s functionality. The signals generated that have been displayed on the scope are satisfactory. Furthermore, the proposed testing system can be used for improving the performance of protective relay.
A High Time Resolution Digital Pulse Width Modulator Based on Field Programmable Gate Array’s Phase Locked Loop Megafunction
The digital pulse width modulator (DPWM) is the crucial building block for digitally-controlled DC-DC switching converter, which converts the digital duty ratio signal into its analog counterpart to control the power MOSFET transistors on or off. With the increase of switching frequency of digitally-controlled DC-DC converter, the DPWM with higher time resolution is required. In this paper, a 15-bits DPWM with three-level hybrid structure is presented; the first level is composed of a7-bits counter and a comparator, the second one is a 5-bits delay line, and the third one is a 3-bits digital dither. The presented DPWM is designed and implemented using the PLL megafunction of FPGA (Field Programmable Gate Arrays), and the required frequency of clock signal is 128 times of switching frequency. The simulation results show that, for the switching frequency of 2 MHz, a DPWM which has the time resolution of 15 ps is achieved using a maximum clock frequency of 256MHz. The designed DPWM in this paper is especially useful for high-frequency digitally-controlled DC-DC switching converters.
Run-Time Customisation of Soft-Core CPUs on Field Programmable Gate Array
The use of customised soft-core processors in which instructions can be integrated into a system in application hardware is increasing in the Field Programmable Gate Array (FPGA) field. Specifically, the partial run-time reconfiguration of FPGAs in specialised processors for a particular domain can be very beneficial. In this report, the design and implementation for the customisation of a soft-core MIPS processor using an FPGA and partial reconfiguration (PR) of FPGA technology will be addressed to achieve efficient resource use. This can be achieved using a PR design flow that helps the design fit into a smaller device. Moreover, the impact of static power consumption could be reduced due to runtime reconfiguration. This will be done by configurable custom instructions implemented in the hardware as an extension on the MIPS CPU. The aim of this project is to investigate the PR of FPGAs for run-time adaptations of the instruction set of a soft-core CPU, including the integration of custom instructions and the exploration of the potential to use the MultiBoot feature available in Xilinx FPGAs to carry out the PR process. The system will be evaluated and tested on a Nexus 3 development board featuring a Xilinx Spartran-6 FPGA. The system will be able to load reconfigurable custom instructions dynamically into user programs with the help of the trap handler when the custom instruction is called by the MIPS CPU. The results of this experiment demonstrate that custom instructions in hardware can speed up a certain function and many instructions can be saved when compared to a software implementation of the same function. Implementing custom instructions in hardware is perfectly possible and worth exploring.
Massively-Parallel Bit-Serial Neural Networks for Fast Epilepsy Diagnosis: A Feasibility Study
There are about 1% of the world population suffering
from the hidden disability known as epilepsy and major developing
countries are not fully equipped to counter this problem. In order to
reduce the inconvenience and danger of epilepsy, different methods
have been researched by using a artificial neural network (ANN)
classification to distinguish epileptic waveforms from normal brain
waveforms. This paper outlines the aim of achieving massive
ANN parallelization through a dedicated hardware using bit-serial
processing. The design of this bit-serial Neural Processing Element
(NPE) is presented which implements the functionality of a complete
neuron using variable accuracy. The proposed design has been tested
taking into consideration non-idealities of a hardware ANN. The NPE
consists of a bit-serial multiplier which uses only 16 logic elements
on an Altera Cyclone IV FPGA and a bit-serial ALU as well as a
look-up table. Arrays of NPEs can be driven by a single controller
which executes the neural processing algorithm. In conclusion, the
proposed compact NPE design allows the construction of complex
hardware ANNs that can be implemented in a portable equipment
that suits the needs of a single epileptic patient in his or her daily
activities to predict the occurrences of impending tonic conic seizures.
Field Programmable Gate Array Based Infinite Impulse Response Filter Using Multipliers
In this paper, an Infinite Impulse Response (IIR) filter
has been designed and simulated on an Field Programmable Gate
Arrays (FPGA). The implementation is based on Multiply Add and
Accumulate (MAC) algorithm which uses multiply operations for
design implementation. Parallel Pipelined structure is used to
implement the proposed IIR Filter taking optimal advantage of the
look up table of target device. The designed filter has been
synthesized on Digital Signal Processor (DSP) slice based FPGA to
perform multiplier function of MAC unit. The DSP slices are useful
to enhance the speed performance. The proposed design is simulated
with Matlab, synthesized with Xilinx Synthesis Tool, and
implemented on FPGA devices. The Virtex 5 FPGA based design can
operate at an estimated frequency of 81.5 MHz as compared to 40.5
MHz in case of Spartan 3 ADSP based design. The Virtex 5 based
implementation also consumes less slices and slice flip flops of target
FPGA in comparison to Spartan 3 ADSP based implementation to
provide cost effective solution for signal processing applications.
Real-Time Image Encryption Using a 3D Discrete Dual Chaotic Cipher
In this paper, an encryption algorithm is proposed for real-time image encryption. The scheme employs a dual chaotic generator based on a three dimensional (3D) discrete Lorenz attractor. Encryption is achieved using non-autonomous modulation where the data is injected into the dynamics of the master chaotic generator. The second generator is used to permute the dynamics of the master generator using the same approach. Since the data stream can be regarded as a random source, the resulting permutations of the generator dynamics greatly increase the security of the transmitted signal. In addition, a technique is proposed to mitigate the error propagation due to the finite precision arithmetic of digital hardware. In particular, truncation and rounding errors are eliminated by employing an integer representation of the data which can easily be implemented. The simple hardware architecture of the algorithm makes it suitable for secure real-time applications.
A High Level Implementation of a High Performance Data Transfer Interface for NoC
The distribution of a single global clock across a chip
has become the major design bottleneck for high performance VLSI
systems owing to the power dissipation, process variability and multicycle
cross-chip signaling. A Network-on-Chip (NoC) architecture
partitioned into several synchronous blocks has become a promising
approach for attaining fine-grain power management at the system
level. In a NoC architecture the communication between the blocks is
handled asynchronously. To interface these blocks on a chip
operating at different frequencies, an asynchronous FIFO interface is
inevitable. However, these asynchronous FIFOs are not required if
adjacent blocks belong to the same clock domain. In this paper, we
have designed and analyzed a 16-bit asynchronous micropipelined
FIFO of depth four, with the awareness of place and route on an
FPGA device. We have used a commercially available Spartan 3
device and designed a high speed implementation of the
asynchronous 4-phase micropipeline. The asynchronous FIFO
implemented on the FPGA device shows 76 Mb/s throughput and a
handshake cycle of 109 ns for write and 101.3 ns for read at the
simulation under the worst case operating conditions (voltage =
0.95V) on a working chip at the room temperature.
FPGA Implementation of RSA Encryption Algorithm for E-Passport Application
Securing the data stored on E-passport is a very important issue. RSA encryption algorithm is suitable for such application with low data size. In this paper the design and implementation of 1024 bit-key RSA encryption and decryption module on an FPGA is presented. The module is verified through comparing the result with that obtained from MATLAB tools. The design runs at a frequency of 36.3 MHz on Virtex-5 Xilinx FPGA. The key size is designed to be 1024-bit to achieve high security for the passport information. The whole design is achieved through VHDL design entry which makes it a portable design and can be directed to any hardware platform.
Evaluation of Features Extraction Algorithms for a Real-Time Isolated Word Recognition System
Paper presents an comparative evaluation of features extraction algorithm for a real-time isolated word recognition system
based on FPGA. The Mel-frequency cepstral, linear frequency cepstral, linear predictive and their cepstral coefficients were
implemented in hardware/software design. The proposed system was investigated in speaker dependent mode for 100 different
Lithuanian words. The robustness of features extraction algorithms was tested recognizing the speech records at different signal to noise rates. The experiments on clean records show highest accuracy for Mel-frequency cepstral and linear frequency cepstral coefficients. For records with 15 dB signal to noise rate the linear predictive cepstral coefficients gives best result. The hard and soft part of the system is clocked on 50 MHz and 100 MHz accordingly. For the classification purpose the pipelined dynamic time warping core was implemented. The proposed word recognition system satisfy the real-time requirements and is suitable for applications in embedded systems.
Modified Montgomery for RSA Cryptosystem
Encryption and decryption in RSA are done by modular exponentiation which is achieved by repeated modular multiplication. Hence efficiency of modular multiplication directly determines the efficiency of RSA cryptosystem. This paper designs a Modified Montgomery Modular Multiplication in which addition of operands is computed by 4:2 compressor. The basic logic operations in addition are partitioned over two iterations such that parallel computations are performed. This reduces the critical path delay of proposed Montgomery design. The proposed design and RSA are implemented on Virtex 2 and Virtex 5 FPGAs. The two factors partitioning and parallelism have improved the frequency and throughput of proposed design.
A Multi Cordic Architecture on FPGA Platform
Coordinate Rotation Digital Computer (CORDIC) is a unique digital computing unit intended for the computation of mathematical operations and functions. This paper presents A multi CORDIC processor that integrates different CORDIC architectures on a single FPGA chip and allows the user to select the CORDIC architecture to proceed with based on what he wants to calculate and his needs. Synthesis show that radix 2 CORDIC has the lowest clock delay, radix 8 CORDIC has the highest LUT usage and lowest register usage while Hybrid Radix 4 CORDIC had the highest clock delay.
Efficient Hardware Architecture of the Direct 2- D Transform for the HEVC Standard
This paper presents the hardware design of a unified
architecture to compute the 4x4, 8x8 and 16x16 efficient twodimensional
(2-D) transform for the HEVC standard. This
architecture is based on fast integer transform algorithms. It is
designed only with adders and shifts in order to reduce the hardware
cost significantly. The goal is to ensure the maximum circuit reuse
during the computing while saving 40% for the number of operations.
The architecture is developed using FIFOs to compute the second
dimension. The proposed hardware was implemented in VHDL. The
VHDL RTL code works at 240 MHZ in an Altera Stratix III FPGA.
The number of cycles in this architecture varies from 33 in 4-point-
2D-DCT to 172 when the 16-point-2D-DCT is computed. Results
show frequency improvements reaching 96% when compared to an
architecture described as the direct transcription of the algorithm.
An FPGA Implementation of Intelligent Visual Based Fall Detection
Falling has been one of the major concerns and threats
to the independence of the elderly in their daily lives. With the
worldwide significant growth of the aging population, it is essential
to have a promising solution of fall detection which is able to operate
at high accuracy in real-time and supports large scale implementation
using multiple cameras. Field Programmable Gate Array (FPGA) is a
highly promising tool to be used as a hardware accelerator in many
emerging embedded vision based system. Thus, it is the main
objective of this paper to present an FPGA-based solution of visual
based fall detection to meet stringent real-time requirements with
high accuracy. The hardware architecture of visual based fall
detection which utilizes the pixel locality to reduce memory accesses
is proposed. By exploiting the parallel and pipeline architecture of
FPGA, our hardware implementation of visual based fall detection
using FGPA is able to achieve a performance of 60fps for a series of
video analytical functions at VGA resolutions (640x480). The results
of this work show that FPGA has great potentials and impacts in
enabling large scale vision system in the future healthcare industry
due to its flexibility and scalability.
Optimized Multiplier Based upon 6-Input Luts and Vedic Mathematics
A new approach has been used for optimized design of multipliers based upon the concepts of Vedic mathematics. The design has been targeted to state-of-the art field-programmable gate arrays (FPGAs). The multiplier generates partial products using Vedic mathematics method by employing basic 4x4 multipliers designed by exploiting 6-input LUTs and multiplexers in the same slices resulting in drastic reduction in area. The multiplier is realized on Xilinx FPGAs using devices Virtex-5 and Virtex-6.Carry Chain Adder was employed to obtain final products. The performance of the proposed multiplier was examined and compared to well-known multipliers such as Booth, Carry Save, Carry ripple, and array multipliers. It is demonstrated that the proposed multiplier is superior in terms of speed as well as power consumption.
FPGA Hardware Implementation and Evaluation of a Micro-Network Architecture for Multi-Core Systems
This paper presents the design, implementation and evaluation of a micro-network, or Network-on-Chip (NoC), based on a generic pipeline router architecture. The router is designed to efficiently support traffic generated by multimedia applications on embedded multi-core systems. It employs a simplest routing mechanism and implements the round-robin scheduling strategy to resolve output port contentions and minimize latency. A virtual channel flow control is applied to avoid the head-of-line blocking problem and enhance performance in the NoC. The hardware design of the router architecture has been implemented at the register transfer level; its functionality is evaluated in the case of the two dimensional Mesh/Torus topology, and performance results are derived from ModelSim simulator and Xilinx ISE 9.2i synthesis tool. An example of a multi-core image processing system utilizing the NoC structure has been implemented and validated to demonstrate the capability of the proposed micro-network architecture. To reduce complexity of the image compression and decompression architecture, the system use image processing algorithm based on classical discrete cosine transform with an efficient zonal processing approach. The experimental results have confirmed that both the proposed image compression scheme and NoC architecture can achieve a reasonable image quality with lower processing time.
Implemented 5-bit 125-MS/s Successive Approximation Register ADC on FPGA
Implemented 5-bit 125-MS/s successive
approximation register (SAR) analog to digital converter (ADC) on
FPGA is presented in this paper.The design and modeling of a high
performance SAR analog to digital converter are based on monotonic
capacitor switching procedure algorithm .Spartan 3 FPGA is chosen
for implementing SAR analog to digital converter algorithm. SAR
VHDL program writes in Xilinx and modelsim uses for showing
Efficient Hardware Implementation of an Elliptic Curve Cryptographic Processor Over GF (2 163)
A new and highly efficient architecture for elliptic curve scalar point multiplication which is optimized for a binary field recommended by NIST and is well-suited for elliptic curve cryptographic (ECC) applications is presented. To achieve the maximum architectural and timing improvements we have reorganized and reordered the critical path of the Lopez-Dahab scalar point multiplication architecture such that logic structures are implemented in parallel and operations in the critical path are diverted to noncritical paths. With G=41, the proposed design is capable of performing a field multiplication over the extension field with degree 163 in 11.92 s with the maximum achievable frequency of 251 MHz on Xilinx Virtex-4 (XC4VLX200) while 22% of the chip area is occupied, where G is the digit size of the underlying digit-serial finite field multiplier.
The Data Processing Electronics of the METIS Coronagraph aboard the ESA Solar Orbiter Mission
METIS is the Multi Element Telescope for Imaging
and Spectroscopy, a Coronagraph aboard the European Space
Agency-s Solar Orbiter Mission aimed at the observation of the solar
corona via both VIS and UV/EUV narrow-band imaging and spectroscopy. METIS, with its multi-wavelength capabilities, will
study in detail the physical processes responsible for the corona heating and the origin and properties of the slow and fast solar wind.
METIS electronics will collect and process scientific data thanks to its detectors proximity electronics, the digital front-end subsystem
electronics and the MPPU, the Main Power and Processing Unit,
hosting a space-qualified processor, memories and some rad-hard
FPGAs acting as digital controllers.This paper reports on the overall
METIS electronics architecture and data processing capabilities
conceived to address all the scientific issues as a trade-off solution between requirements and allocated resources, just before the
Preliminary Design Review as an ESA milestone in April 2012.
Spacecraft Neural Network Control System Design using FPGA
Designing and implementing intelligent systems has become a crucial factor for the innovation and development of better products of space technologies. A neural network is a parallel system, capable of resolving paradigms that linear computing cannot. Field programmable gate array (FPGA) is a digital device that owns reprogrammable properties and robust flexibility. For the neural network based instrument prototype in real time application, conventional specific VLSI neural chip design suffers the limitation in time and cost. With low precision artificial neural network design, FPGAs have higher speed and smaller size for real time application than the VLSI and DSP chips. So, many researchers have made great efforts on the realization of neural network (NN) using FPGA technique. In this paper, an introduction of ANN and FPGA technique are briefly shown. Also, Hardware Description Language (VHDL) code has been proposed to implement ANNs as well as to present simulation results with floating point arithmetic. Synthesis results for ANN controller are developed using Precision RTL. Proposed VHDL implementation creates a flexible, fast method and high degree of parallelism for implementing ANN. The implementation of multi-layer NN using lookup table LUT reduces the resource utilization for implementation and time for execution.
FPGA Implement of a Vision Based Lane Departure Warning System
Using vision based solution in intelligent vehicle application often needs large memory to handle video stream and image process which increase complexity of hardware and software. In this paper, we present a FPGA implement of a vision based lane departure warning system. By taking frame of videos, the line gradient of line is estimated and the lane marks are found. By analysis the position of lane mark, departure of vehicle will be detected in time. This idea has been implemented in Xilinx Spartan6 FPGA. The lane departure warning system used 39% logic resources and no memory of the device. The average availability is 92.5%. The frame rate is more than 30 frames per second (fps).
FPGA based Relative Distance Measurement using Stereo Vision Technology
In this paper, we propose a novel concept of relative
distance measurement using Stereo Vision Technology and discuss
its implementation on a FPGA based real-time image processor. We
capture two images using two CCD cameras and compare them.
Disparity is calculated for each pixel using a real time dense disparity
calculation algorithm. This algorithm is based on the concept of
indexed histogram for matching. Disparity being inversely
proportional to distance (Proved Later), we can thus get the relative
distances of objects in front of the camera. The output is displayed on
a TV screen in the form of a depth image (optionally using pseudo
colors). This system works in real time on a full PAL frame rate (720
x 576 active pixels @ 25 fps).
An Innovative Wireless Sensor Network Protocol Implementation using a Hybrid FPGA Technology
Traditional development of wireless sensor network
mote is generally based on SoC1 platform. Such method of
development faces three main drawbacks: lack of flexibility in terms
of development due to low resource and rigid architecture of SoC;
low capability of evolution and portability versus performance if
specific micro-controller architecture features are used; and the rapid
obsolescence of micro-controller comparing to the long lifetime of
power plants or any industrial installations. To overcome these
drawbacks, we have explored a new approach of development of
wireless sensor network mote using a hybrid FPGA technology. The
application of such approach is illustrated through the
implementation of an innovative wireless sensor network protocol
FPGA Implementation of a Vision-Based Blind Spot Warning System
Vision-based intelligent vehicle applications often require large amounts of memory to handle video streaming and image processing, which in turn increases complexity of hardware and software. This paper presents an FPGA implement of a vision-based blind spot warning system. Using video frames, the information of the blind spot area turns into one-dimensional information. Analysis of the estimated entropy of image allows the detection of an object in time. This idea has been implemented in the XtremeDSP video starter kit. The blind spot warning system uses only 13% of its logic resources and 95k bits block memory, and its frame rate is over 30 frames per sec (fps).
Real-Time Digital Oscilloscope Implementation in 90nm CMOS Technology FPGA
This paper describes the design of a real-time audiorange
digital oscilloscope and its implementation in 90nm CMOS
FPGA platform. The design consists of sample and hold circuits,
A/D conversion, audio and video processing, on-chip RAM, clock
generation and control logic. The design of internal blocks and
modules in 90nm devices in an FPGA is elaborated. Also the key
features and their implementation algorithms are presented.
Finally, the timing waveforms and simulation results are put