Design Optimization Methodology of CMOS Active Mixers for Multi-Standard Receivers
A design flow of multi-standard down-conversion
CMOS mixers for three modern standards: Global System Mobile,
Digital Enhanced Cordless Telephone and Universal Mobile
Telecommunication Systems is presented. Three active mixer-s
structures are studied. The first is based on the Gilbert cell which
gives a tolerable noise figure and linearity with a low conversion
gain. The second and third structures use the current bleeding and
charge injection techniques in order to increase the conversion gain.
An improvement of about 2 dB of the conversion gain is achieved
without a considerable degradation of the other characteristics. The
models used for noise figure, conversion gain and IIP3 used are
studied. This study describes the nature of trade-offs inherent in such
structures and gives insights that help in identifying which structure
is better for given conditions.
Active mixer, Radio-frequency transceiver, Multistandardfront end, Gilbert cell, current bleeding, charge injection.
High Order Cascade Multibit ΣΔ Modulator for Wide Bandwidth Applications
A wideband 2-1-1 cascaded ΣΔ modulator with a
single-bit quantizer in the two first stages and a 4-bit quantizer in the
final stage is developed. To reduce sensitivity of digital-to-analog
converter (DAC) nonlinearities in the feedback of the last stage,
dynamic element matching (DEM) is introduced. This paper presents
two modelling approaches: The first is MATLAB description and the
second is VHDL-AMS modelling of the proposed architecture and
exposes some high-level-simulation results allowing a behavioural
study. The detail of both ideal and non-ideal behaviour modelling are
presented. Then, the study of the effect of building blocks
nonidealities is presented; especially the influences of nonlinearity,
finite operational amplifier gain, amplifier slew rate limitation and
capacitor mismatch. A VHDL-AMS description presents a good
solution to predict system-s performances and can provide sensitivity
curves giving the impact of nonidealities on the system performance.
behavioural study, DAC nonlinearity, DEM, ΣΔ
modulator, VHDL-AMS modelling.
Design of Folded Cascode OTA in Different Regions of Operation through gm/ID Methodology
This paper presents an optimized methodology to
folded cascode operational transconductance amplifier (OTA) design.
The design is done in different regions of operation, weak inversion,
strong inversion and moderate inversion using the gm/ID methodology
in order to optimize MOS transistor sizing.
Using 0.35μm CMOS process, the designed folded cascode OTA
achieves a DC gain of 77.5dB and a unity-gain frequency of 430MHz
in strong inversion mode. In moderate inversion mode, it has a 92dB
DC gain and provides a gain bandwidth product of around 69MHz.
The OTA circuit has a DC gain of 75.5dB and unity-gain frequency
limited to 19.14MHZ in weak inversion region.
CMOS IC design, Folded Cascode OTA, gm/ID
A 24-Bit, 8.1-MS/s D/A Converter for Audio Baseband Channel Applications
This paper study the high-level modelling and design
of delta-sigma (ΔΣ) noise shapers for audio Digital-to-Analog
Converter (DAC) so as to eliminate the in-band Signal-to-Noise-
Ratio (SNR) degradation that accompany one channel mismatch in
audio signal. The converter combines a cascaded digital signal
interpolation, a noise-shaping single loop delta-sigma modulator with
a 5-bit quantizer resolution in the final stage. To reduce sensitivity of
Digital-to-Analog Converter (DAC) nonlinearities of the last stage, a
high pass second order Data Weighted Averaging (R2DWA) is
introduced. This paper presents a MATLAB description modelling
approach of the proposed DAC architecture with low distortion and
swing suppression integrator designs. The ΔΣ Modulator design can
be configured as a 3rd-order and allows 24-bit PCM at sampling rate
of 64 kHz for Digital Video Disc (DVD) audio application. The
modeling approach provides 139.38 dB of dynamic range for a 32
kHz signal band at -1.6 dBFS input signal level.
DVD-audio, DAC, Interpolator and Interpolation
Filter, Single-Loop ΔΣ Modulation, R2DWA, Clock Jitter
High Level Characterization and Optimization of Switched-Current Sigma-Delta Modulators with VHDL-AMS
Today, design requirements are extending more and
more from electronic (analogue and digital) to multidiscipline design.
These current needs imply implementation of methodologies to make
the CAD product reliable in order to improve time to market, study
costs, reusability and reliability of the design process.
This paper proposes a high level design approach applied for the
characterization and the optimization of Switched-Current Sigma-
Delta Modulators. It uses the new hardware description language
VHDL-AMS to help the designers to optimize the characteristics of
the modulator at a high level with a considerably reduced CPU time
before passing to a transistor level characterization.
high level design, optimization, switched-Current
Sigma-Delta Modulators, VHDL-AMS.