Open Science Research Excellence

ICHCE 2020 : International Conference on Hardware and Computer Engineering

Sydney, Australia
March 26 - 27, 2020

Conference Code: 20AU03ICHCE

Conference Proceedings

All submitted conference papers will be blind peer reviewed by three competent reviewers. The peer-reviewed conference proceedings are indexed in the Open Science Index, Google Scholar, Semantic Scholar, Zenedo, OpenAIRE, BASE, WorldCAT, Sherpa/RoMEO, and other index databases. Impact Factor Indicators.

Special Journal Issues

ICHCE 2020 has teamed up with the Special Journal Issue on Hardware and Computer Engineering. A number of selected high-impact full text papers will also be considered for the special journal issues. All submitted papers will have the opportunity to be considered for this Special Journal Issue. The paper selection will be carried out during the peer review process as well as at the conference presentation stage. Submitted papers must not be under consideration by any other journal or publication. The final decision for paper selection will be made based on peer review reports by the Guest Editors and the Editor-in-Chief jointly. Selected full-text papers will be published online free of charge.

Conference Sponsor and Exhibitor Opportunities

The Conference offers the opportunity to become a conference sponsor or exhibitor. To participate as a sponsor or exhibitor, please download and complete the Conference Sponsorship Request Form.

Important Dates

Abstracts/Full-Text Paper Submission Deadline   February 27, 2020
Notification of Acceptance/Rejection   March 12, 2020
Final Paper (Camera Ready) Submission & Early Bird Registration Deadline   February 28, 2020
Conference Dates   March 26 - 27, 2020

Important Notes

Please ensure your submission meets the conference's strict guidelines for accepting scholarly papers. Downloadable versions of the check list for Full-Text Papers and Abstract Papers.

Please refer to the Paper Submission GUIDE before submitting your paper.

Selected Conference Papers

1) Evaluating the Impact of Replacement Policies on the Cache Performance and Energy Consumption in Different Multicore Embedded Systems
Sajjad Rostami-Sani, Mojtaba Valinataj, Amir-Hossein Khojir-Angasi
2) Verification and Proposal of Information Processing Model Using EEG-Based Brain Activity Monitoring
Toshitaka Higashino, Naoki Wakamiya
3) The Fluid Limit of the Critical Processor Sharing Tandem Queue
Amal Ezzidani, Abdelghani Ben Tahar, Mohamed Hanini
4) Single Event Transient Tolerance Analysis in 8051 Microprocessor Using Scan Chain
Jun Sung Go, Jong Kang Park, Jong Tae Kim
5) CPU Architecture Based on Static Hardware Scheduler Engine and Multiple Pipeline Registers
Ionel Zagan, Vasile Gheorghita Gaitan
6) Improving the Performances of the nMPRA Architecture by Implementing Specific Functions in Hardware
Ionel Zagan, Vasile Gheorghita Gaitan
7) IntelliCane: A Cane System for Individuals with Lower-Limb Mobility and Functional Impairments
Adrian Bostan, Nicolae Tapus, Adriana Tapus
8) Parallel Vector Processing Using Multi Level Orbital DATA
Nagi Mekhiel
9) Massively-Parallel Bit-Serial Neural Networks for Fast Epilepsy Diagnosis: A Feasibility Study
Si Mon Kueh, Tom J. Kazmierski
10) Design of Local Interconnect Network Controller for Automotive Applications
Jong-Bae Lee, Seongsoo Lee
11) Innovative Power Engineering in a Selected Rural Commune
Pawel Sowa, Joachim Bargiel
12) Performance Evaluation of a Prioritized, Limited Multi-Server Processor-Sharing System That Includes Servers with Various Capacities
Yoshiaki Shikata, Nobutane Hanayama
13) 3A Distributed Method Algorithm for Exact Side Load Managing Smart Grid Using LABVIEW
N. Ravi Kumar, R. Kamalakannan
14) Simulation of Utility Accrual Scheduling and Recovery Algorithm in Multiprocessor Environment
A. Idawaty, O. Mohamed, A. Z. Zuriati
15) A Methodology for the Synthesis of Multi-Processors
Hamid Yasinian

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